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M65KA128AL
128Mbit (4 Banks x 2M x 16) 1.8V Supply, Low Power SDRAMs
Feature summary
128Mbit Synchronous Dynamic RAM - Organized as 4 Banks of 2 MWords, each 16 bits wide Supply Voltage - VDD = 1.65V to 1.95V - VDDQ = 1.65 to 1.95V for Input/Output Synchronous Burst Read and Write - Fixed Burst lengths: 1, 2, 4, 8 words or full Page - Burst Types: Sequential and Interleaved. - Maximum clock frequency: 104MHz - CAS Latency 2, 3 Automatic Precharge Low Power features: - PASR (Partial Array Self Refresh), - Automatic TCSR (Temperature Compensated Self Refresh) - Driver Strength (DS) - Deep Power-Down Mode Delivery form: Unsawn Wafer Auto Refresh and Self Refresh LVCMOS Interface Compatible with Multiplexed Addressing Operating temperature - -25C to +90C
Wafer

The M65KA128AL is only available as part of a Multi-Chip Package Product.
April 2006
Rev 3
1/53
www.st.com 1
Contents
M65KA128AL
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Address Inputs (A0-A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank Select Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lower/Upper Data Input/Output Mask (LDQM/UDQM) . . . . . . . . . . . . . . 10 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 4.4 Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Extended Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bank (Row) Activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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M65KA128AL
Contents
4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14
Write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Auto Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Self Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Deep Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 5.2 Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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List of tables
M65KA128AL
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Self Refresh Current (IDD6) Values in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . 25 Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Asynchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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M65KA128AL
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chip Enable Signal During Read, Write and Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read with Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read with Auto Precharge AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Clock Suspend During Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Random Column Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Random Row Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Column Interleaved Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Burst Column Read Followed by Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . 35 Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Byte Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Mode Register Set AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock Suspend During Burst Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Random Column Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Random Row Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Column Interleaved Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Burst Column Write Followed by Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . 43 Precharge Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power-Down Mode and Clock Masking AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Deep Power-Down Entry AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Deep Power-Down Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Summary description
M65KA128AL
1
Summary description
The M65KA128AL is a 128 Mbit Low Power Synchronous DRAM (SDRAM) organized as 4 Banks of 2,097,152 Words of 16 bits each. The Low Power SDRAM achieves low power consumption and high-speed data transfer using the pipeline architecture. It is well suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers. The device architecture is illustrated in Figure 2: Functional Block Diagram. The device uses Burst mode to read and write data. It is capable of one, two, four, eight-word and full page, sequential and interleaved Burst. To minimize current consumption during self-refresh operations, the M65KA128AL includes three system-accessible mechanisms configured via the Extended Mode Register:

Automatic Temperature Compensated Self Refresh (TCSR) is used to adapts the refresh rate according to the operating temperature. Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of bank, one bank, two banks or all banks. The Deep Power-Down (DPD) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array.
The M65KA128AL is programmable through two registers, the Mode Register and the Extended Mode Register:
The Mode Register is used to select the CAS Latency, the Burst Type (sequential or interleaved) and the Burst Length. For more details, refer to Table 4: Mode Register Definition, and to Section 4.1: Mode Register Set command. The Extended Mode Register is used to program the Low Power features (PASR and Driver Strength) to reduce the current consumption during the Self Refresh operations. For more details, refer to Table 5: Extended Mode Register Definition, and to Section 4.2: Extended Mode Register Set command.
The M65KA128AL is offered in unsawn wafer.
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M65KA128AL Figure 1. Logic Diagram
VDD VDDQ 12 A0-A11 2 BA0-BA1 E RAS CAS K KE W UDQM LDQM M65KA128AL 16
Summary description
DQ0-DQ15
VSS VSSQ
AI12138
Table 1.
A0-A11 BA0-BA1 DQ0-DQ15 K KE E W RAS CAS UDQM LDQM VDD VDDQ VSS VSSQ
Signal Names
Address Inputs Bank Select Inputs Data Inputs/Outputs Clock Input Clock Enable Input Chip Select Input Write Enable Input Row Address Strobe Input Column Address Strobe Input Upper Data Input/Output Mask Lower Data Input/Output Mask Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground
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Summary description Figure 2. Functional Block Diagram
PASR Extended Mode Register K KE E State Machine RAS CAS W UDQM LDQM Row Active Self Refresh Logic & Timer Internal Row Counter Row PreDecoders 2 M x 16 Bank 3 2 M x 16 Bank 2 2 M x 16 Bank 1 Sense AMP & I/O Gate 2 M x 16 Bank 0 Memory Cell Array Column Decoders Bank Select Column Add Counter ... Row Decoders Row Decoders Row Decoders
M65KA128AL
Refresh Column Active
I/O Buffer & Logic
DQ0 ...
Row Decoders
...
Column PreDecoders
DQ15
Address Registers Address Buffers Burst Counter Burst Length
A0-A11/BA0-BA1
Mode Register
CAS Latency
Data Out Control
ai08974d
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M65KA128AL
Signal descriptions
2
Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A11)
The A0-A11 Address Inputs are used to select the row or column to be made active. If a row is selected, all A0-A11 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2
Bank Select Inputs (BA0-BA1)
The BA0 and BA1 Banks Select Inputs are used to select the bank to be made active. The device must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH, when selecting the addresses. The address inputs are latched on the rising edge of the clock signal, K.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read operation, or are used to input the data during a write operation.
2.4
Chip Select (E)
The Chip Select input E activates the memory state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and BA1-BA0, to select the starting column location prior to a Read or Write.
2.6
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and BA1-BA0, to select the starting address location prior to a Read or Write.
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
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Signal descriptions
M65KA128AL
2.8
Clock Input (K)
The Clock signal, K, is used to clock the Read and Write cycles. During normal operation, the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL.
2.9
Clock Enable (KE)
The Clock Enable, KE, pin is used to control the synchronizing of the signals to Clock signal K. The signals are clocked when KE is High, VIH When KE is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KE is also involved in switching the device to the Self Refresh, Power-Down and Deep Power-Down modes.
2.10
Lower/Upper Data Input/Output Mask (LDQM/UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to control the Input and Output buffers, respectively. During Read operations, LDQM and UDQM control the Output buffer. When both LDQM and UDQM are High, VIH, the Output buffer is disabled. When held Low, VIL, the Output buffer is enabled. LDQM and UDQM are used to mask the data read or written from or to the memory array. LDQM Low, VIL, gates the data from or to the Lower Byte Data I/O (DQ0 to DQ7) while UDQM Low, gates the data from or to the Upper Byte Data I/Os (DQ8 to DQ15). During read operations, the latency between LDQM/UDQM High or Low and data output disabled or enabled is two clock cycles. During write operations, there is no latency between LDQM/UDQM stable and data input valid.
2.11
VDD Supply Voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read and Write).
2.12
VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid certain conditions that would result in data corruption.
2.13
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system ground.
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M65KA128AL
Signal descriptions
2.14
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package).
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Operations
M65KA128AL
3
Operations
There are 7 operating modes that control the memory. Each of these is described in this section, see Table 2: Operating Modes, for a summary.
3.1
Power-Up
The Low Power SDRAM has to be powered up and initialized in a well determined manner: 1. 2. 3. Power must be applied to VDD and VDDQ simultaneously. After applying VDD and VDDQ, a minimum pause of 200s must be respected before the signals can be toggled. The Precharge command must then be issued to all banks. The Clock Enable input, KE, and UDQM/LDQM must be held High until the Precharge command is issued to make sure that DQ0-DQ15 remain high impedance. tRP after precharging all the banks, the Mode Register and the Extended Mode Register must be set by issuing a Mode Register Set command and an Extended Mode Register Set command, respectively. A minimum pause of tMRD must be respected after each register set command. After configuring the registers, 2 or more Auto Refresh cycles must be executed before the device is ready for normal operation.
4.
5.
The fourth and fifth steps can be swapped.
3.2
Burst Read
The Read Command is used to switch the device to Burst Read mode (see Section 4.4: Read command for details). In Burst Read mode the data is output in bursts synchronized with the clock. A valid Burst Read operation is initiated by driving E and CAS Low, VIL, and by driving W and RAS High, VIH, at the positive edge of the clock signal, K. Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Burst Read command is issued, the Burst Read operation will be followed by an Auto Precharge cycle. During Burst Read operation, the memory reads data from the activated bank. Different Burst Types and Lengths can be programmed using the Mode Register bits (see Section 5.1: Mode Register description). The Burst Types available are Sequential and Interleaved, selected using Mode Register Bit A3. Possible Burst Lengths are 1-, 2-, 4-, 8Word and Full Page, selected using Mode Register Bits A2 to A0.
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M65KA128AL
Operations
3.3
Burst Write
The Write Command is used to switch the device to Burst Write mode (see Section 4.5: Write command for details). In Burst Write mode the data is input in bursts synchronized with the clock. A valid Burst Write is initiated by driving E, CAS and W Low, VIL, and by driving RAS High, VIH, at the positive edge of the clock signal, K. Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Write command is issued, the Write operation will be followed by an Auto Precharge cycle. During Burst Write operation, the memory writes data to the activated bank. As for Burst Read, different Burst Types and Lengths can be utilized, programmed in the same fashion.
3.4
Self Refresh
In Self Refresh mode, the data contained in the Low Power SDRAM memory array is retained and refreshed. The Low Power SDRAM refresh cycles are asynchronous. The Self-Refresh mode is entered by driving KE Low (set to `0'), with E, RAS, and CAS Low, and W High (set to `1'). When in this mode, the device is not clocked any more. The Self Refresh mode is exited by driving KE from Low to High, with E High, RAS, CAS and W Don't Care, or with E Low and RAS, CAS and W High.
3.5
Auto Refresh
The Auto Refresh mode is used to refresh the Low Power SDRAM in normal operation mode whenever needed. During an auto refresh operation, KE must be kept High, VIH and the address bits are "Don't Care" because the specific address bits are generated by the internal refresh address counter.
3.6
Power-Down
In Power-Down mode, the current is reduced the Standby current. For the memory to enter the Power-Down mode, KE must be held Low (set to `0'), after the Precharge Time tRP, with E High (set to `1'), RAS, CAS and W Don't Care, or with E Low, RAS, CAS and W High. The Power-Down mode is exited by driving KE High, with E High, RAS, CAS and W Don't Care, or with E Low and RAS, CAS and W High.
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Operations
M65KA128AL
3.7
Deep Power-Down
The purpose of this mode is to achieve maximum power reduction by cutting the power supply to the whole memory array. Data is no longer retained when the device enters Deep Power-Down Mode. The Low Power SDRAM is switched to Deep Power-Down mode by applying VIL to E and W, and VIH to RAS and CAS on the rising edge of the clock, K, and by driving KE Low, VIL. For more information, see Figure 25: Deep Power-Down Entry AC Waveforms. The Low Power SDRAM is released from Deep Power-Down mode by applying VIH to KE, with all other pins Don't Care. Then a special sequence, is required before the device can take any new command into account: 1. 2. 3. 4. Maintain No Operation status conditions (see Table 3 for a minimum time of 200s, Issue a Precharge command to all the banks of the device (see Section 4.6: Precharge command for details), Issue 2 or more Auto-Refresh commands, Issue a Mode Register Set command and an Extended Mode Register Set command to initialize the Mode Register and the Extended Mode Register, respectively.
The third and fourth steps can be swapped. The Deep Power-Down mode exit sequence is illustrated in Figure 26: Deep Power-Down Exit AC Waveforms. Table 2. Operating Modes (1)
KEn-1 VIH KEn X E VIL RAS VIH CAS VIL W VIH A10 VIL A9, A11 Valid A0-A7 Start Column Address Start Column Address BA0-BA1 Bank Select
Operating Mode Burst Read
Burst Write Self Refresh Auto Refresh Power-Down Deep Power-Down Device Deselect No Operation
VIH VIH VIH VIH VIH VIH VIH
X VIL VIH VIL VIL X X
VIL VIL VIL VIL VIH VIL VIH VIL
VIH VIL VIL VIH X VIH X VIH
VIL VIL VIL VIH X VIH X VIH
VIL VIH VIH VIH X VIL X VIH
VIL
Valid X X X X
Bank Select X X X X
X
X X
X
X
1. X = Don't Care VIL or VIH.
14/53
M65KA128AL
Commands
4
Commands
There are 16 commands that control the memory. Refer to Table 3: Commands, in conjunction with the text descriptions below and to Table 3: Commands.
4.1
Mode Register Set command
The Mode Register Set command is issued by applying VIL to E, RAS, CAS and W and by setting BA1 to `0', and BA0 to `0'. The Mode Register Set command must be executed after the Power-Up sequence prior to issuing a Bank (Row) Active command. The execution of a Mode Register Set command will re-program the Mode Register, modifying its contents.
4.2
Extended Mode Register Set command
The Extended Mode Register Set command is issued by applying VIL to E, RAS, CAS and W, and then by setting BA1 to `1', and BA0 to `0'. The Extended Mode Register Set command must be executed after the Power-Up sequence prior to issuing a Bank (Row) Active command. The execution of an Extended Mode Register Set command will re-program the Extended Mode Register, modifying its contents.
4.3
Bank (Row) Activate command
The Bank (Row) Active command is used to activate a row in a specific bank of the device. This command is initiated by driving E and RAS Low, VIL, and driving CAS and W High, VIH, at the positive edge of the clock signal, K. The value on BA1 and BA0 selects the bank, and the value on A0-A11 selects the row. The selected row remains active for column access until a Precharge command is issued to the bank containing the row. A minimum time of tRCD is required after issuing the Bank (Row) Active command prior to initiating Read and Write operations from and to the activated bank.
15/53
Commands
M65KA128AL
4.4
Read command
The Read command is used to switch the Low Power SDRAM to Burst Read mode (see Section 3.2: Burst Read). During Burst Read operation, the memory reads data from the activated bank. Inputs BA1 and BA0 are used to select a bank, Address inputs A8-A0 are used to select a starting column location. The value at input A10 determines whether Auto Precharge is activated. If Auto Precharge is selected, the row being accessed will be precharged at the end of the Burst Read operation. If Auto Precharge is not selected, the row will remain active for subsequent accesses. Different Burst Types and Lengths can be programmed using the Mode Register bits (see Table 4: Mode Register Definition):

The Burst Types available are Sequential and Interleaved selected using Mode Register Bit MR3. Possible Burst Lengths are 1-, 2-, 4-, 8-Word and Full Page, selected using Mode Register Bits MR0 to MR2.
4.5
Write command
The Write command is used to switch the Low Power SDRAM to Burst Write mode (see Section 3.3: Burst Write). During Burst Write operation, the memory writes data to the activated bank. Inputs BA1 and BA0 inputs are used to select a bank, the A8-A0 Address Inputs are used to select a starting column location. The value at the A10 input determines whether Auto Precharge is activated. If Auto Precharge is selected, the row being accessed will be precharged at the end of the Write burst. If Auto Precharge is not selected, the row will remain active for subsequent accesses. Burst Types and Lengths apply to Burst Write operation in the same manner as they do to Burst Read operations.
4.6
Precharge command
The Precharge command is used to close the open row in a particular bank, or the open rows in all the banks, depending on the value on the A10 Address Input. If A10 is High, at VIH, when the Precharge command is issued, the command will be applied to all the banks, closing all the open rows in these banks. If A10 is Low, at VIL, when the Precharge command is issued, the command will be applied only to the selected bank, closing the open row of this bank. The Precharge command can also be used to terminate a Burst. Issued during a Burst Read or Burst Write cycle, the Precharge command will interrupt the Burst operation and close the active bank. The precharge command can be issued any time after tRAS min. is satisfied. Soon after the precharge command is issued, the precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The tRP parameter is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is CL-1 clock cycles before the reference clock that indicates the last data word is valid (see Figure 5)
16/53
M65KA128AL
Commands
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL (min.) specification defines the earliest time that a precharge command can be issued. After the Precharge command is issued, a minimum time of tRP is required before the bank(s) are available.
4.7
Auto Precharge command
The Auto Precharge command is used to close the open row in a specific bank after a Read or Write cycle. Read or Write with Auto Precharge is initiated if the A10 Address Input is High, at VIH, when a Read or Write command is issued.
4.8
Burst Terminate command
The Burst Terminate command is used to terminate a Burst operation. A Burst operation can be interrupted by using the Precharge command (see the Section 4.6: Precharge command for details), or by issuing the Burst Terminate command. Issuing the Burst Terminate command during a Burst Read or Write cycle will terminate the burst while leaving the bank open.
4.9
Data Mask command
The Data Mask command is used to mask the Read or Write data. A Data Mask command issued during a Read cycle will disable the data outputs, switching them to the highimpedance state after a delay of two clock cycles. A Data Mask command issued during a Write cycle will disable the data inputs with no delay.
4.10
Clock Suspend command
The Clock Suspend command is used to interrupt the internal clock of the Low Power SDRAM. The command is controlled by the Clock Enable input, KE, which is High, VIH, in normal access mode. The Clock Suspend command is issued by driving KE Low, VIL thus freezing the internal clock and extending data Read and Write cycles.
4.11
Power-Down command
The Power-Down command is used to put the device in Power-Down mode where the operating current is reduced to the Standby current. All banks must be precharged and a minimum time of tRP must elapse before issuing the Power-Down command.
4.12
Auto Refresh command
The Auto Refresh command is used to put the device in Auto refresh mode (see Section 3.5: Auto Refresh).
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Commands
M65KA128AL
4.13
Self Refresh command
The purpose of the Self Refresh command is used to put the device in Self Refresh mode to retain and refresh the data contained in the Low Power SDRAM memory array. In Self Refresh mode, the Low Power SDRAM runs Refresh cycles asynchronously. The Self Refresh cycle is performed according to the Extended Mode Register settings:

EMR3 to EMR4 bits configure the Refresh rate at which the memory array is refreshed to perform a Temperature Compensated Self Refresh. EMR0 to EMR2 configure the part of the memory array being refresh (Partial Array Self Refresh).
4.14
Deep Power-Down command
The Deep Power-Down command is used to switch the Low Power SDRAM to Deep PowerDown Mode. This mode provides maximum power reduction as it cuts the power of the entire memory array of the device. For more information on how the command is issued and its exit sequence, see Section 3.7: Deep Power-Down, Figure 25: Deep Power-Down Entry AC Waveforms, and Figure 26: Deep Power-Down Exit AC Waveforms.
Table 3.
Command
Commands(1)
KEn-1 KEn E RAS CAS W UDQM LDQM A10 A9, A11 A0-A7 BA0BA1 DQ0DQ7 X X Bank Select Bank Select Bank Select Bank Select Bank Select Bank Select Bank Select Bank Select X Output Valid Output Valid DQ8DQ15 X X X
Mode Register Set(2) Extended Mode Register Set(2) Bank (Row) Active Word Read/Read with Auto Precharge Upper Byte Read/Read with Auto Precharge Lower Byte Read/Read with Auto Precharge Word Write/Write with Auto Precharge Upper Byte Write/Write with Auto Precharge Lower Byte Write/Write with Auto Precharge Write with Auto Precharge
VIH VIH VIH
X X X
VIL VIL VIL
VIL VIL VIL
VIL VIL VIH
VIL VIL VIH
X X X
X X X
Op Code Op Code Start Row Address VIL/VIH
(3)
VIH
X
VIL
VIH
VIL
VIH
VIL
VIL
X
Start Column Address Start Column Address Start Column Address Start Column Address Start Column Address Start Column Address Start Column Address
VIH
X
VIL
VIH
VIL
VIH
VIL
VIH
VIL/VIH
(3)
X
Hi-Z
VIH
X
VIL
VIH
VIL
VIH
VIH
VIL
VIL/VIH
(3)
X
Output Valid
Hi-Z
VIL
VIL
VIL/VIH
(3)
X
Input Valid Input Valid
VIH
X
VIL
VIH
VIL
VIL
VIL
VIH
VIL/VIH
(3)
X
Hi-Z
VIH
VIL
VIL/VIH
(3)
X
Input Valid
Hi-Z
VIH
X
VIL
VIH
VIL
VIL
VIH
X
X
X
18/53
M65KA128AL Table 3.
Command Precharge All Banks Precharge Selected Bank Burst Terminate Auto Refresh Self Refresh Entry Self Refresh Exit(4) Power-Down Entry(5)(6) Power-Down Exit(5)(6) Deep PowerDown Entry Deep PowerDown Exit Clock Suspend Entry Clock Suspend Exit Data Mask / Output Enable Data Mask / Output Disable
Commands
Commands(1) (continued)
KEn-1 KEn E RAS CAS W UDQM LDQM A10 A9, A11 A0-A7 BA0BA1 X V X X X X X X DQ0DQ7 X X X X X X X X DQ8DQ15 X X X X X X X X
VIH VIH VIH VIH VIH
X X VIH VIH VIL
VIL VIL VIL VIL VIL VIH VIL VIL VIH VIL VIH VIL
VIL VIL VIH VIL VIL X VIH VIH X VIH X VIH X
VIH VIH VIH VIL VIL X VIH VIH X VIH X VIH
VIL VIL VIL VIH VIH X
X X X X X
X X X X X
VIH VIL X X X X
X X
VIL
VIH
X VIH VIH X VIH X VIL X X X X X X X X X X X X VIL VIH X X
X X X X
VIH
VIL
VIL
VIH
X
X
X
X
X
VIH VIL VIH VIL VIH VIH
VIL VIH VIL VIH X X
X X X X VIL VIH
X X X X X X
X X X X X X
X X X X X Hi-Z
X X X X X Hi-Z
X X X X
X X X X
1. X = Don't Care VIL or VIH. V = Valid. 2. BA1 and BA0 must both be driven Low, VIL, to issue the Mode Register Set command. BA1 and BA0 must be driven High, VIH and Low, VIL, respectively, to issue the Extended Mode Register Set Command. 3. To perform Read or Write operations with Autoprecharge, A10 must be held High, VIH. 4. The Self Refresh mode is exited by asynchronously driving KE from Low to High. 5. The Power-Down mode is exited by asynchronously driving KE from Low to High. 6. Banks must be precharged before issuing a Power-Down command.
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Register descriptions
M65KA128AL
5
5.1
Register descriptions
Mode Register description
The Mode Register is used to select the CAS Latency (1, 2 or 3), the Burst Type (sequential, interleaved), and the Burst Length (1-, 2-, 4-, 8-Word width or full page). It is loaded by issuing a Mode Register Set command that programs A0 to A11 address bits. The values placed on the address lines are then latched into the Mode Register. BA0-BA1 must be set to `0'. See Table 4: Mode Register Definition, for more details.
Table 4.
Address Bits A11-A7
Mode Register Definition
Mode Register Bit Register Description Value 00000 010 2 Clock Cycles 3 Clock Cycles Bit Description
A6-A4
MR6-MR4
CAS Latency Bits 011
Other configurations reserved 0 A3 MR3 Burst Type 1 000 001 010 A2-A0 MR2-MR0 Burst Length Bit 011 111 Interleaved 1 Word (A3 is Don't Care) 2 Words (A3 is Don't Care) 4 Words (A3 is Don't Care) 8 Words (A3 is Don't Care) Full Page if A3 Low Reserved if A3 High Sequential
Other configurations reserved BA1-BA0 00
20/53
M65KA128AL
Register descriptions
5.2
Extended Mode Register description
The Extended Mode Register is used to program Low Power self-refresh operation of the device (PASR, DS, TCSR). It is used to select the area of the memory array refreshed during Partial Array Self Refresh operations, and the driver strength. It is loaded by issuing a Extended Mode Register Set command that programs A0 to A11 address bits. The values placed on the address lines are then latched into the Extended Mode Register. BA0 and BA1 must be set to `0' and `1' respectively. See Table 5: Extended Mode Register Definition, for more details.
Table 5.
Address Bits A11-A10
Extended Mode Register Definition
Mode Register Bit Register Description Auto Temperature Compensated Self Refresh (ATCSR) 00 0 1 00 00 Full Strength 1/2 Strength 1/4 Strength 1/8 Strength Enabled Reserved Value Bit Description
A9
EMR9
A8-A7
-
A6-A5
EMR6-EMR5
Driver Strength Bits
01 10 11
A4-A3
EMR4-EMR3
00 000 All Banks Two Banks (BA1=0) One Banks (BA0 and BA1 =0)
A2-A0
EMR2-EMR0
Self Refresh Area Bits
001 010
Other configurations reserved BA1-BA0 10
21/53
Maximum rating
M65KA128AL
6
Maximum rating
Stressing the device above the ratings listed in Table 6: Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute Maximum Ratings
Value Symbol TJ TSTG VIO VDD, VDDQ IOS PD Parameter Min Junction Temperature Storage Temperature Input or Output Voltage Supply Voltage Short Circuit Output Current Power Dissipation -25 -55 -0.5 -0.5 50 1 Max 90 125 2.6 2.6 C C V V mA W Unit
22/53
M65KA128AL
DC and AC parameters
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 7: Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating and AC Measurement Conditions
Parameter(1)(2) Min Supply Voltage (VDD) Input/Output Supply Voltage (VDDQ Junction Temperature (TJ) Load Capacitance (CL) Output Impedance (Z0) Input Rise/Fall Time (tR, tF) Input High Voltage (VIH) Input Low Voltage (VIL) Input and Output Timing Ref. Voltages Output Transition Timing Reference Voltages
1. All voltages are referenced to VSS = 0V. 2. TJ = -25 to 90C, f = 1MHz 3. VDDQ must not exceed the level of VDD.
M65KA128AL Units Typ 1.8 1.8 Max 1.95 1.95 90 30 50 1 1.6 0.2 VDDQ/2 0.3VDDQ 0.7VDDQ V V C pF
1.65 )(3) 1.65 -25
ns V V V V
Figure 3.
AC Measurement I/O Waveform
I/O Timing Reference Voltage VDDQ VDDQ/2 0V
Output Transition Timing Reference Voltage VDDQ 0.7VDDQ 0.3VDDQ
AI08009
0V
23/53
DC and AC parameters Table 8. AC Measurement Load Circuit
M65KA128AL
DEVICE UNDER TEST
OUT Z0 CL
CL includes probe capacitance
AI08008c
Table 9.
Symbol CI1
Capacitance(1)(2)
M65KA128AL Parameter Pin Min K Input Capacitance A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM DQ0-DQ15 2.0 2.0 6.0 Max 3.5 3.8 7.5 pF pF pF Unit
CI2 CIO Data I/O Capacitance
1. TJ = 25C, f = 1MHz 2. Sampled only, not 100% tested.
Table 10.
Symbol ILI ILO(2) VIL VIH VOL VOH
DC Characteristics 1
Parameter Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition(1) 0VVIN 1.8V 1.8V 0V VOUT VIN = 0V VIN = 0V IOUT = 100A, VIN = 0V IOUT = -100A, VIN = 0V VDDQ - 0.2 M65KA128AL Unit Min -1 -1.5 -0.3(3) 0.8VDDQ Max 1 1.5 0.3 VDDQ + 0.3(4) 0.2 A A V V V V
1. TJ = -25 to 90C. 2. Data outputs are disabled. 3. VIL may undershoot to -1.0V for less that 5ns. 4. VIH may overshoot to 2.6V for less that 5ns.
24/53
M65KA128AL Table 11.
Symbol IDD1(2) IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4(2) IDD5(3)(4) IDD6 IDD7 Active Standby Current in PowerDown Mode
DC and AC parameters
DC Characteristics 2
Parameter Operating Current Test Condition(1) Burst length = 1, one bank active tRC tRC(min), IOL = 0mA KE VIL(max), tCK = 15ns Standby Current in Power-Down Mode KE VIL(max), tCK = Input signal stable KE VIH (min), E VIH (min), tCK = 15ns Input signals are changed once in 30ns KE VIH (min), tCK = Input signals are stable KE VIL(max), tCK = 15ns KE VIL(max), tCK = Typ 36 0.6 mA 0.5 3 mA 1 1 mA 0.8 15 mA 5 35 52 65 See Table 12. 10 mA mA mA A A Unit mA
Standby Current in Non Power-Down Mode
KE VIH (min), E VIH (min), tCK = 15ns Active Standby Current in Non Power- Input signals are changed once in 30ns Down Mode KE V (min), t =
IH CK
Input signals are stable Burst Mode Current, CL=2 Burst Mode Current, CL=3 Auto Refresh Current, CL=2 Auto Refresh Current, CL=3 Self Refresh Current tCK tCK (min), IOL = 0mA All banks active tRC1 tRC1(min) KE 0.2V
See Figure 25: Deep Power-Down Entry Standby Current in Deep Power-down AC Waveforms, and Figure 26: Deep Mode Power-Down Exit AC Waveforms.
1. TJ = -25 to 90C. 2. IDD1 and IDD4 depend on the output loading and cycle rates. All measurements are made with the output open and on condition that the addresses are changed only once during tCK(min.). 3. The minimum value of tRC (RAS cycle time for Refresh operation) is shown in Table 14: Asynchronous AC Characteristics. 4. IDD5 is measured on condition that the addresses are changed only once during tCK (min.).
Table 12.
Self Refresh Current (IDD6) Values in Normal Operating Mode(1)
4 Banks Temperature Typ. TJ < 40C 40C < TJ 70C 70C TJ 90C Max. 150 200 600 Typ. Max. 130 170 350 Typ. Max. 120 150 220 A A A 2 Banks 1 Bank Unit
1. VDD = 1.8V, VDDQ = 1.8V, VSS = 0V, KE 0.2V.
25/53
DC and AC parameters Table 13.
Symbol tAC tAS tAH tCK tCS tCH tCHW tCLW tCKS tCKSP tCKH tDS tDH tOH tOLZ tOHZ
M65KA128AL
Synchronous AC Characteristics
Parameter Access Time From Clock CAS Latency = 2 Address Setup Time Address Hold Time CAS Latency = 3 Clock Period CAS Latency = 2 Command Setup Time Command Hold Time Clock High Pulse Width Clock Low Pulse Width Clock Enable Setup Time Clock Enable Setup Time (Power-Down Exit) Clock Enable Hold Time Data Input Setup Time Data Input Hold Time Data Output Hold Time Clock to Data Output Low-Z CAS Latency = 3 Clock to Data Output High-Z CAS Latency = 2 3 9 ns 15 2 1 3 3 2 2 1 2 1 3 0 3 7 ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1 9.6 9 ns ns ns ns Test Condition CAS Latency = 3 Min Max 7 Unit ns
26/53
M65KA128AL Table 14.
Symbol tDPL tDAL tDQZ tDQM tMRD tRC tRCD tRAS tRP tRRD tRC1 tRC2
(2)
DC and AC parameters
Asynchronous AC Characteristics
M65KA128AL Parameter Min Data Input Valid to Precharge Command Data Input Valid to Bank/Row Activate Command UDQM or LDQM High to Data Output Hi-Z UDQM or LDQM High to Data Input Masked Mode Register Set Cycle Time RAS Cycle Time Delay Time, RAS Active to CAS Active RAS Active Time RAS Precharge Time Delay Time, RAS Active to RAS Bank Active Auto Refresh Exit Time Self Refresh Exit Time Refresh Time Transition Time Delay Time, Write Command to Data Input 1 0 2 86 28.5 57 28.5 2 105 105 64 30 120,000 CAS Latency = 3 CAS Latency = 2 2 2CLK + 28.5 2CLK + 30 2 0 Max tCK ns ns tCK tCK tCK ns ns ns ns tCK ns ns ms ns tCK Unit(1)
tREF t tWTL
1. The unit tCK is the system Clock cycle time. 2. A new command can be issued tRC after the Self Refresh mode is exited.
27/53
DC and AC parameters Figure 4.
T21
M65KA128AL
Chip Enable Signal During Read, Write and Precharge
AI09959b
T19
T20
T17
T18
CAb
T16
T15
T14
T13
DAb2
DAb3
DAb4
T11
T12
T10
T9
T8
T7
T6
CAa
QAa1
QAa2
QAa3
QAa4 DQN
T3
T0
High
1. The Chip Enable signal, E, must be issued at a minimum rate with respect to the other signals. 2. Burst Length = 4 Words, Latency = 3 clock cycles. 3. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A, DAan= Data n written to Column a in Bank A.
28/53
DQ0-DQ15
Address
LDQM/ UDQM
RAS
CAS
BA0
BA1
A10
KE
W
K
E
Hi-Z
Low
Bank/Row Activate in Bank A
T2
Low
T1
Low
RAa
RAa
Read from Bank A
T4
T5
Write in Bank A
DAb1
Precharge Bank A
M65KA128AL Figure 5.
tCK K tCHW KE tCKS E tCS RAS tCH tCKH tCLW
DC and AC parameters
Read with Precharge AC Waveforms
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CAS
W
BA0
BA1
A10
Address tAS LDQM/ UDQM tAH Low
tAC DQ0-DQ15 Hi-Z
DQN DQN+1 DQN+2 DQN+3
tOHZ
tRCD tRAS
tOLZ
tOH tRP tRC
Bank/Row Activate in Bank A
Read from Bank A
Precharge in Bank A
Bank/Row Activate in Bank A
AI09934c
1. Burst Length = 4 Words, Latency = 3 clock cycles.
29/53
DC and AC parameters Figure 6. Read with Auto Precharge AC Waveforms
Auto Precharge Start from Bank C T0 tCK K tCHW KE tCKS E tCS RAS tCH tCKH tCLW T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
M65KA128AL
T12
T13
CAS
W
BA0
BA1
A10
Address tAS LDQM/ UDQM Low tAH tAC Hi-Z
DQN DQN+1 DQN+2 DQN+3
tOH
DQ0-DQ15
tRCD
tOLZ tRAS, tRRD tRC
tOHZ
Bank/Row Activate in Bank C
Read with Auto Precharge from Bank C
Bank/Row Activate in Bank D
Bank/Row Activate in Bank C
AI09935c
1. Burst Length = 4 Words, Latency = 3 clock cycles.
30/53
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T15 T16 T17
T13
T14
Figure 7.
M65KA128AL
K
KE
E
RAS
1. Burst Length = 4 Words, Latency = 3 clock cycles.
CAS
W
BA0
Clock Suspend During Burst Read AC Waveforms
BA1
A10
RAa
Address RAa CAa
LDQM/ UDQM Low Hi-Z
DQ0-DQ15
QAa1
QAa2
QAa3
QAa4
Hi-Z
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
Read from Bank A Clock Suspended during 1 cycle Clock Suspended during 2 cycles Clock Suspended during 3 cycles End of Read
AI09947
DC and AC parameters
Bank/Row Activate in Bank A
31/53
32/53
T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
Figure 8.
T0
T1
K
High
DC and AC parameters
KE
E
RAS
1. Burst Length = 4 Words, Latency = 3 clock cycles.
CAS
Random Column Read AC Waveforms
W
BA0
BA1
A10
RAa
RAa
Address
RAa
CAa
CAb
CAc
RAa
CAa
LDQM/ UDQM QAa1 QAa2
Low
DQ0-DQ15
Hi-Z
QAa3
QAa4 DQN
QAb1
QAb2
QAc1
QAc2
QAc3
QAc4
Bank/Row Activate in Bank A
Read from Bank A
Read from Bank A
Read from Bank A
Precharge in Bank A
Bank/Row Activate in Bank A
Read from Bank A
AI09955
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
M65KA128AL
Figure 9.
M65KA128AL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
KE
E
RAS
1. Burst Length = 8 Words, Latency = 3 clock cycles.
CAS
Random Row Read AC Waveforms
W
BA0
BA1
A10
RBa
RAa
RBb
Address
RBa
CBa
RAa
CAa
RBb
CBb
LDQM/ UDQM QBa1 QBa2
Low
DQ0-DQ15
Hi-Z
QBa3 QBa4
QBa5 QBa6 QBa7
QBa8
QAa1
QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Bank/Row Activate in Bank B
Read from Bank B
Bank/Row Activate in Bank A
Read from Bank A
Precharge in Bank B
Bank/Row Activate in Bank B
Read from Bank A
AI09957
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from row m in Bank A.
DC and AC parameters
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T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RDa CAa RDa CDa CDb CDc CAb QAa1 DQN QAa2 QAa3 QAa4 QDa1 QDa2 QDb1 QDb2 QDc1 QDc2 QAb1 QAb2 QAb3 QAb4 Read from Bank A Bank/Row Activate in Bank D Read from Bank D Read from Bank D Read from Bank D Read from Bank A Precharge in Bank D Precharge in Bank A
AI09520b
T0
T1
K
High
DC and AC parameters
KE
E
RAS
1. Burst Length = 4 Words, Latency = 3 clock cycles.
CAS
W
Figure 10. Column Interleaved Read AC Waveforms
BA0
BA1
A10
RAa
Address
RAa
LDQM/ UDQM
Low
Hi-Z
DQ0-DQ15
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
Bank/Row Activate in Bank A
M65KA128AL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
M65KA128AL
K
High
KE
E
RAS
1. Burst Length = 4 Words, Latency = 3 clock cycles.
RDa RDb CAa RDa CDa CAb RDb CDb
DQN
CAS
W
BA0
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
Read from Bank A Bank/Row Activate in Bank D Read + Auto Precharge from Bank D Read + Auto Precharge from Bank A Auto Precharge from Bank D Bank/Row Activate in Bank D Read + Auto Precharge from Bank D Autoprecharge Start from Bank A
AI09961b
BA1
A10
RAa
Address
RAa
Figure 11. Burst Column Read Followed by Auto Precharge AC Waveforms
LDQM/ UDQM
Low
Hi-Z
DQ0-DQ15
DC and AC parameters
Bank/Row Activate in Bank A
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T0 K tCKS KE tCH, tAH E tCS, tAS RAS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 CAS W BA0 BA1 A10 Address LDQM/ UDQM Low tDH DQ0-DQ15 tDS tRCD tRRD tRC tRCD tRAS tRC Bank/Row Activate in Bank C Bank/Row Activate in Bank B Write to Bank B Auto Precharge Start from Bank C Precharge in Bank B Bank/Row Activate in Bank C Bank/Row Activate in Bank B Hi-Z
DQN
1. Burst Length = 4 Words.
tDAL tDPL tRP Write + Auto Precharge to Bank C
AI09947
DC and AC parameters M65KA128AL
Figure 12. Write AC Waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K High
M65KA128AL
KE
1. Burst Length = 4 Words.
Hi-Z Hi-Z tDQZ Lower Byte Read Upper Byte Read Upper Byte Write Lower Byte Write Read from Bank D Upper Byte Write Upper Byte Read Upper Byte Read
AI09963c
E
RAS
CAS
Figure 13. Byte Write AC Waveforms
W
BA0
BA1
A10
Address
LDQM
UDQM
DQ0-DQ7
DQ8-DQ15
DC and AC parameters
Bank/Row Activate Read in Bank D from Bank D
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DC and AC parameters Figure 14. Mode Register Set AC Waveforms
T0 K High KE tMRD, 2 Clock Cycles (min) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
M65KA128AL
T12
T13
E
RAS
CAS
W
BA0
BA1
A10
Address
MR
Data (2)
LDQM/ UDQM
DQ0-DQ15
Hi-Z tRP Precharge All Banks Mode Register Set Bank/Row Activate Valid
AI09948
1. To program the Extended Mode Register, BA0 and BA1 must be set to `0' and `1' respectively, and A0 to A11 to the Extended Mode Register Data. 2. MR Data is the value to be written to the Mode Register.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
M65KA128AL
K
KE
E
RAS
CAS
W
BA0
Figure 15. Clock Suspend During Burst Write AC Waveforms
BA1
A10
RAa
Address RAa CAa
LDQM/ UDQM Low Hi-Z DAa1 DAa2
DQ0-DQ15
DAa3
DAa4
1. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAan= Data n Written to Column a in Bank A.
Write to Bank A Clock Suspended during 1 cycle Clock Suspended during 2 cycles Clock Suspended during 3 cycles
AI09950
DC and AC parameters
Bank/Row Activate in Bank A
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T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RDd CDa CDb CDc RDd CDd DDa1 DDa2 DDa3 DDa4 DQN DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 DDd2 Write to Bank D Write to Bank D Write to Bank D Precharge in Bank D Bank/Row Activate in Bank D Write to Bank D
AI09956b
T0
T1
K
1. Burst Length = 4 Words.
DC and AC parameters
High
KE
E
RAS
CAS
Figure 16. Random Column Write AC Waveforms
W
BA0
BA1
A10
RDa
Address
RDa
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
2. RDa = Address of Row a in Bank D, CDa = Address of Column a in Bank D, DDmn= Data n written to Column m in Bank D.
M65KA128AL
Bank/Row Activate in Bank D
M65KA128AL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
1. Burst Length = 8 Words.
RDa RAb CAa RDa CDa RAb CAb DAa1 DAa3 DAa2 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 Write to Bank A Bank/Row Activate in Bank D Write to Bank D Precharge in Bank A Bank/Row Activate in Bank A Write to Bank A
AI09958
High
KE
E
RAS
CAS
Figure 17. Random Row Write AC Waveforms
W
BA0
BA1
A10
RAa
Address
RAa
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to row m in Bank A.
DC and AC parameters
Bank/Row Activate in Bank A
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T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RBa CAa RBa CBa CBb CBc CAb CBd
DQN DAa1
T0
T1
K
High
1. Burst Length = 4 Words.
DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DBc1 DBc2 DAb1 DAb2 DBb1 DBb2 DBb3 DBb4 Write to Bank A Bank/Row Activate in Bank B Write to Bank B Write to Bank B Write to Bank B Write to Bank A Write to Bank B Precharge in Bank A Precharge in Bank B
AI09521b
DC and AC parameters
KE
E
RAS
CAS
W
Figure 18. Column Interleaved Write AC Waveforms
BA0
BA1
A10
RAa
Address
RAa
LDQM/ UDQM
Low
Hi-Z
DQ0-DQ15
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to Column m in Bank A.
Bank/Row Activate in Bank A
M65KA128AL
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
M65KA128AL
K
High
1. Burst Length = 4 Words
RDa RDb CAa RDa CDa CAb RDb CDb
DQN
KE
E
RAS
CAS
W
BA0
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
Bank/Row Activate in Bank D Write to Bank A Write + Auto Precharge from Bank D Write + Auto Precharge from Bank A Auto Precharge Start from Bank D Bank/Row Write + Activate Auto Precharge in Bank D from Bank D Auto Precharge Start from Bank A
AI09962b
BA1
A10
RAa
Address
RAa
Figure 19. Burst Column Write Followed by Auto Precharge AC Waveforms
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
DC and AC parameters
Bank/Row Activate in Bank A
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T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 RAb RAc CAa Write Masking RAb CAb RAc DAa1 tRCD tDPL tRAS Write to Bank A Precharge in Bank A + Write Terminated Bank/Row Activate in Bank A DAa2 DAa3 DQDAa4 N DAa5 tRP tRAS Read from Bank A Precharge in Bank A + Read Terminated Bank/Row Activate in Bank A
AI09524
T0
T1
K
High
DC and AC parameters
KE
E
Figure 20. Precharge Termination
RAS
1. Burst Length = 8 Words, Latency = 3 clock cycles.
QAb1 QAb2 QAb3 DQQAb4 N
CAS
W
BA0
BA1
A10
RAa
Address
RAa
LDWM/ UDQM
DQ0-DQ15
Hi-Z
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A, DAan= Data n written to Column a in Bank A.
M65KA128AL
Bank/Row Activate in Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
M65KA128AL
K
1 Clock Cycle needed 2 Refresh Cycles needed tMRD tMRD
High Level nedeed
KE
E
Figure 21. Power-On Sequence
RAS
CAS
W
1
BA0
BA1
A10
Address
MR Data (1)
EMR Data (1)
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRP tRC1 CBR Auto Refresh tRC1 Bank/Row Activate
AI09960b
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Precharge All Banks Mode Extended Mode CBR Register Set Register Set Auto Refresh
DC and AC parameters
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T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 tCKSP tCKSP RAa RAa CAa QAa1 QAa2 QAa3 QAa4 Bank/Row Activate in Bank A Power-Down Entry Power-Down Exit Read from Bank A Start of Clock Masking End of Clock Masking Precharge in Bank A Power-Down Entry Power-Down Exit ACTIVE STANDBY PRECHARGE STANDBY
AI09951
K
KE
DC and AC parameters
E
RAS
1. Burst Length = 4 Words, Latency = 3 clock cycles.
CAS
W
BA0
BA1
Figure 22. Power-Down Mode and Clock Masking AC Waveforms
A10
Address
LDQM/ UDQM
Low
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
DQ0-DQ15
Hi-Z
M65KA128AL
T0
T1
T2
T3
T4
T5
T6
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6
Tm+7
M65KA128AL
K
High
KE
Figure 23. Auto Refresh
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/ UDQM
Low
DQ0-DQ15 tRC1
Hi-Z tRC1 Auto Refresh Bank/Row Activate Read
AI09952c
tRP
DC and AC parameters
Precharge
Auto Refresh
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T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tk Tk+1 Tk+2 Tk+3 Tk+4 tRP tRC2 tRC2 Self Refresh Exit Bank/Row Activate Self Refresh Exit Self Refresh Entry (or Bank/Row Activate) Next Clock Enable Next Clock Enable
AI09953b
T0
K
DC and AC parameters
KE
Figure 24. Self Refresh
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
M65KA128AL
Precharge (optional)
Self Refresh Entry
M65KA128AL Figure 25. Deep Power-Down Entry AC Waveforms
T0 K T1 T2 T3 T4
DC and AC parameters
T5
KE
E
RAS
CAS
W
A10
DQ0-DQ15
Hi-Z tRP Precharge All Banks (optional) Deep Power-Down Entry
ai07720c
1. BA0, BA1 and address bits A0 to A11 (except A10) are `Don't Care'.
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1
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T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 2 Refresh Cycles needed tMRD tMRD
MR Data (1) EMR Data (1)
T0
K
1 Clock Cycle needed
High Level nedeed
DC and AC parameters
KE
E
RAS
CAS
W
Figure 26. Deep Power-Down Exit AC Waveforms
BA0
BA1
A10
Address
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z 200s tRP tRC1 Auto Refresh (optional) tRC1 Bank/Row Activate
AI09954c
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Precharge All Banks (optional) Mode Extended Mode Auto Refresh Register Set Register Set (optional) (optional) (optional)
M65KA128AL
Deep Power-Down Exit
M65KA128AL
Part numbering
8
Table 15.
Example:
Part numbering
Ordering Information Scheme
M65KA128AL 10 W 5
Device Type M65 = Low Power SDRAM
Delivery Form K = Wafer Form
Operating Voltage, Mode, Bus Width A = VDD = VDDQ = 1.8V, Standard LPSDRAM, x16
Array Organization 128 = 4 Banks x 2Mbit x 16
Option 1 A = One Chip Enable
Option 2 L = L Die
Speed Class 10 = 10ns
Package W = Unsawn Wafer
Temperature Range 5 = -25 to 90C
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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Revision history
M65KA128AL
9
Revision history
Table 16.
Date 28-Nov-2005 05-Jan-2006 28-Apr-2006
Document revision history
Revision 1 2 3 First Issue. Wafer and die specifications section removed. Datasheet status updated to Full Datasheet. Changes
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M65KA128AL
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